Normal view MARC view ISBD view

Routing Congestion in VLSI Circuits: Estimation and Optimization [electronic resource] / by Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar.

By:

Contributor(s):

Material type:

Subject(s):

LOC classification:

Online resources:

In: Springer eBooks

Tags from this library: No tags from this library for this title. Log in to add tags.

Average rating: 0.0 (0 votes)

Holdings
Item type	Current library	Call number	URL	Copy number	Status	Notes	Barcode
Libro Electrónico	Biblioteca Digital Colección Digital	TK7874.75 S29 2007 (Browse shelf(Opens below))	Link to resource	1	Available	Springerlink	BDIG00012282

Previous								Next
Previous	TK7874.75 G54 2006 VLSI-SOC: From Systems to Chips	TK7874.75 L56 2008 Practical Problems in VLSI Physical Design Automation	TK7874.75 P35 2005 Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings /	TK7874.75 S29 2007 Routing Congestion in VLSI Circuits: Estimation and Optimization	TK7874.75 V68 2006 Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings /	TK7874.75 W55 2008 Digital VLSI Design with Verilog	TK7874.78 E45 2007 Radio Frequency Integrated Circuits and Technologies	Next

There are no comments on this title.

to post a comment.